Infineon TRAVEO T2G - 14.2.15 FLASHC_CM0_STATUS

Technical Reference Manual 002-29852 Rev. *B
14.2.15 FLASHC_CM0_STATUS
Description:
CM0+ interface status
Address:
0x40240460
Offset:
0x460
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] WORK
_INTE
RNAL_ERR
[1:1]
MAIN_INTE
RNAL_ERR
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 MAIN_INTERNAL_ERR RW1C W1S 0 Specifies/registers the occurrence of a FLASH macro
main interface internal error (typically the result of a
read access while a program erase operation is
ongoing) as a result of a CM0+ access (or debug
access via SYS_AP/CM0_AP).
SW clears this field to '0'. HW sets this field to '1' on a
FLASH macro main interface internal error. Typically,
SW reads this field after a code section to detect the
occurrence of an error.
Note: this field is independent of
FLASH_CTL.MAIN_ERR_SILENT.
1 WORK_INTERNAL_ERR RW1C W1S 0 See CM0_STATUS.MAIN_INTERNAL_ERROR.
952
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers