Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.3 CANFD_CH_DBTP
Description:
Data Bit Timing & Prescaler Register
Address:
0x4052000C
Offset:
0xC
Retention:
Retained
IsDeepSleep:
No
Comment:
Protected Write
Default:
0xA33
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DTSEG2 [7:4] DSJW [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:13] DTSEG1 [12:8]
Bits 23 22 21 20 19 18 17 16
Name TDC [23:23] None [22:21] DBRP [20:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 DSJW RW R 3 Data (Re)Synchronization Jump Width
0x0-0xF Valid values are 0 to 15. The actual
interpretation by the hardware of this value is
such that one more than the value programmed here is
used.
4:7 DTSEG2 RW R 3 Data time segment after sample point
0x0-0xF Valid values are 0 to 15. The actual
interpretation by the hardware of this value is
such that one more than the programmed value is
used.
8:12 DTSEG1 RW R 10 Data time segment before sample point
0x00-0x1F Valid values are 0 to 31. The actual
interpretation by the hardware of this value is
such that one more than the programmed value is
used.
16:20 DBRP RW R 0 Data Bit Rate Prescaler
0x00-0x1F The value by which the oscillator frequency
is divided for generating the bit time
quanta. The bit time is built up from a multiple of this
quanta. Valid values for the Bit
Rate Prescaler are 0 to 31. The actual interpretation by
the hardware of this value is
such that one more than the value programmed here is
used.
23 TDC RW R 0 Transmitter Delay Compensation
0= Transmitter Delay Compensation disabled
1= Transmitter Delay Compensation enabled
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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