Infineon TRAVEO T2G - 9.3.18.5 DW_CH_STRUCT_INTR

Technical Reference Manual 002-29852 Rev. *B
9.3.18.5 DW_CH_STRUCT_INTR
Description:
Interrupt
Address:
0x40288010
Offset:
0x10
Retention:
Not Retained
IsDeepSleep:
No
Comment:
The register fields are not retained. This is to ensure that they come up as '0' after coming out
of DeepSleep system power mode.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] CH [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 CH RW1C RW1S 0 Set to '1', when event (as specified by
CH_STATUS.INTR_CAUSE) is detected. Write
INTR.CH field with '1', to clear bit. Write INTR_SET.CH
field with '1', to set bit.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers