Infineon TRAVEO T2G - 9.3.16 DW_CRC_REM_CTL

Technical Reference Manual 002-29852 Rev. *B
9.3.16 DW_CRC_REM_CTL
Description:
CRC remainder control
Address:
0x40280140
Offset:
0x140
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name REM_XOR [7:0]
Bits 15 14 13 12 11 10 9 8
Name REM_XOR [15:8]
Bits 23 22 21 20 19 18 17 16
Name REM_XOR [23:16]
Bits 31 30 29 28 27 26 25 24
Name REM_XOR [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 REM_XOR RW R 0 Specifies a mask with which the
CRC_LFSR_CTL.LFSR32 register is XOR'd to
produce a remainder. The XOR is performed before
remainder reversal.
877
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers