Infineon TRAVEO T2G - 5.1.36 CPUSS_RAM_PWR_DELAY_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.36 CPUSS_RAM_PWR_DELAY_CTL
Description:
Power up delay used for all SRAM power domains
Address:
0x402013C0
Offset:
0x13C0
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x96
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name UP [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] UP [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:9 UP RW R 150 Number clock cycles delay needed after power domain
power up
738
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers