Infineon TRAVEO T2G - 21.25 PPU_FX 8; 21.26 PPU_FX 9; 21.27 PPU_FX 10; 21.28 PPU_FX 11

Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
PERI_MS_PPU_FX7_MS_ATT3
0x400109FC FULL Master attributes 3
21.25 PPU_FX 8
Register Name Address Permission Description
PERI_MS_PPU_FX8_SL_ADDR
0x40010A00 FULL Slave region, base address
PERI_MS_PPU_FX8_SL_SIZE
0x40010A04 FULL Slave region, size
PERI_MS_PPU_FX8_SL_ATT0
0x40010A10 FULL Slave attributes 0
PERI_MS_PPU_FX8_SL_ATT1
0x40010A14 FULL Slave attributes 1
PERI_MS_PPU_FX8_SL_ATT2
0x40010A18 FULL Slave attributes 2
PERI_MS_PPU_FX8_SL_ATT3
0x40010A1C FULL Slave attributes 3
PERI_MS_PPU_FX8_MS_ADDR
0x40010A20 FULL Master region, base address
PERI_MS_PPU_FX8_MS_SIZE
0x40010A24 FULL Master region, size
PERI_MS_PPU_FX8_MS_ATT0
0x40010A30 FULL Master attributes 0
PERI_MS_PPU_FX8_MS_ATT1
0x40010A34 FULL Master attributes 1
PERI_MS_PPU_FX8_MS_ATT2
0x40010A38 FULL Master attributes 2
PERI_MS_PPU_FX8_MS_ATT3
0x40010A3C FULL Master attributes 3
21.26 PPU_FX 9
Register Name Address Permission Description
PERI_MS_PPU_FX9_SL_ADDR
0x40010A40 FULL Slave region, base address
PERI_MS_PPU_FX9_SL_SIZE
0x40010A44 FULL Slave region, size
PERI_MS_PPU_FX9_SL_ATT0
0x40010A50 FULL Slave attributes 0
PERI_MS_PPU_FX9_SL_ATT1
0x40010A54 FULL Slave attributes 1
PERI_MS_PPU_FX9_SL_ATT2
0x40010A58 FULL Slave attributes 2
PERI_MS_PPU_FX9_SL_ATT3
0x40010A5C FULL Slave attributes 3
PERI_MS_PPU_FX9_MS_ADDR
0x40010A60 FULL Master region, base address
PERI_MS_PPU_FX9_MS_SIZE
0x40010A64 FULL Master region, size
PERI_MS_PPU_FX9_MS_ATT0
0x40010A70 FULL Master attributes 0
PERI_MS_PPU_FX9_MS_ATT1
0x40010A74 FULL Master attributes 1
PERI_MS_PPU_FX9_MS_ATT2
0x40010A78 FULL Master attributes 2
PERI_MS_PPU_FX9_MS_ATT3
0x40010A7C FULL Master attributes 3
21.27 PPU_FX 10
Register Name Address Permission Description
PERI_MS_PPU_FX10_SL_ADDR
0x40010A80 PRIVILEGE
- WRITE
Slave region, base address
PERI_MS_PPU_FX10_SL_SIZE
0x40010A84 PRIVILEGE
- WRITE
Slave region, size
PERI_MS_PPU_FX10_SL_ATT0
0x40010A90 PRIVILEGE
- WRITE
Slave attributes 0
PERI_MS_PPU_FX10_SL_ATT1
0x40010A94 PRIVILEGE
- WRITE
Slave attributes 1
PERI_MS_PPU_FX10_SL_ATT2
0x40010A98 PRIVILEGE
- WRITE
Slave attributes 2
PERI_MS_PPU_FX10_SL_ATT3
0x40010A9C PRIVILEGE
- WRITE
Slave attributes 3
PERI_MS_PPU_FX10_MS_ADDR
0x40010AA0 PRIVILEGE
- WRITE
Master region, base address
PERI_MS_PPU_FX10_MS_SIZE
0x40010AA4 PRIVILEGE
- WRITE
Master region, size
PERI_MS_PPU_FX10_MS_ATT0
0x40010AB0 PRIVILEGE
- WRITE
Master attributes 0
PERI_MS_PPU_FX10_MS_ATT1
0x40010AB4 PRIVILEGE
- WRITE
Master attributes 1
PERI_MS_PPU_FX10_MS_ATT2
0x40010AB8 PRIVILEGE
- WRITE
Master attributes 2
PERI_MS_PPU_FX10_MS_ATT3
0x40010ABC PRIVILEGE
- WRITE
Master attributes 3
21.28 PPU_FX 11
1161
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers