Infineon TRAVEO T2G - 5.1.26 CPUSS_CM0_VECTOR_TABLE_BASE

Technical Reference Manual 002-29852 Rev. *B
5.1.26 CPUSS_CM0_VECTOR_TABLE_BASE
Description:
CM0+ vector table base
Address:
0x40201120
Offset:
0x1120
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:0]
Bits 15 14 13 12 11 10 9 8
Name ADDR24 [15:8]
Bits 23 22 21 20 19 18 17 16
Name ADDR24 [23:16]
Bits 31 30 29 28 27 26 25 24
Name ADDR24 [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
8:31 ADDR24 RW 0 Address of CM0+ vector table. This register is used for
CM0+ warm boot purposes: the CM0+ warm boot code
uses the register to initialize the CM0+ internal VTOR
register.
Note: the CM0+ vector table is at an address that is a
256 B multiple.
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2022-04-18
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