Infineon TRAVEO T2G - 15.25.3 GPIO_VDD_INTR

Technical Reference Manual 002-29852 Rev. *B
15.25.3 GPIO_VDD_INTR
Description:
Supply detection interrupt register
Address:
0x40314014
Offset:
0x4014
Retention:
Retained
IsDeepSleep:
No
Comment:
An interrupt cause is cleared (set to '0') by writing a '1' to the corresponding bit field. It is not
recommended to write 0xFF to clear all interrupt causes, as a new interrupt cause may have
occurred between reading the register and clearing. Note that the interrupt cause fields and
the associated interrupt provide DeepSleep functionality (interrupt causes can be set to '1' and
cause the system to wake up from DeepSleep power mode). This register is set whenever a
supply ramp up or ramp down is detected. Some bits may be set after system power-up,
depending on power supply sequencing.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name VDDIO_ACTIVE [7:0]
Bits 15 14 13 12 11 10 9 8
Name VDDIO_ACTIVE [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name VDDD
_ACTIVE
[31:31]
VDDA
_ACTIVE
[30:30]
None [29:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0:15 VDDIO_ACTIVE RW1C A 0 Supply state change detected.
'0': No change to supply detected
'1': Change to supply detected
30 VDDA_ACTIVE RW1C A 0 Same as VDDIO_ACTIVE for the analog supply
VDDA.
31 VDDD_ACTIVE RW1C A 0 The VDDD supply is always present during operation
so a supply transition can not occur. This bit will
always read back '1'.
992
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers