Infineon TRAVEO T2G - 23.9.6 SCB_SPI_STATUS

Technical Reference Manual 002-29852 Rev. *B
23.9.6 SCB_SPI_STATUS
Description:
SPI status
Address:
0x40600024
Offset:
0x24
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] SPI_EC
_BUSY
[1:1]
BUS_BUSY
[0:0]
Bits 15 14 13 12 11 10 9 8
Name CURR_EZ_ADDR [15:8]
Bits 23 22 21 20 19 18 17 16
Name BASE_EZ_ADDR [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 BUS_BUSY R W Undefined SPI bus is busy. The bus is considered busy ('1')
during an ongoing transaction. For Motorola and
National submodes, the busy bit is '1', when the slave
selection is activated. For TI submode, the busy bit is
'1' from the time the preceding/coinciding slave select
is activated for the first transmitted data frame, till the
last MOSI/MISO bit of the last data frame is
transmitted.
1 SPI_EC_BUSY R W Undefined Indicates whether the externally clocked logic is
potentially accessing the EZ memory and/or updating
BASE_ADDR or CURR_ADDR (this is only possible in
EZ mode). This bit can be used by SW to determine
whether BASE_ADDR and CURR_ADDR are reliable.
8:15 CURR_EZ_ADDR R W Undefined SPI current EZ address. Current address pointer. This
field is only reliable in internally clocked mode. In
externally clocked mode the field may be unreliable
(during an ongoing transfer when SPI_EC_BUSY is
'1'), as clock domain synchronization is not performed
in the design.
16:23 BASE_EZ_ADDR R W Undefined SPI base EZ address. Address as provided by a SPI
write transfer. This field is only reliable in internally
clocked mode. In externally clocked mode the field
may be unreliable, as clock domain synchronization is
not performed in the design.
1395
2022-04-18
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