Infineon TRAVEO T2G - 19.5.1.18.7 PASS_SAR_CH_INTR_MASK

Technical Reference Manual 002-29852 Rev. *B
19.5.1.18.7 PASS_SAR_CH_INTR_MASK
Description:
Interrupt mask register.
Address:
0x40900818
Offset:
0x18
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] GRP
_OVERF
LOW
_MASK
[2:2]
GRP
_CANCE
LLED
_MASK
[1:1]
GRP
_DONE_
MASK [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:11] CH
_OVERFL
OW_MASK
[10:10]
CH_PULSE
_MASK
[9:9]
CH
_RANGE_
MASK [8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 GRP_DONE_MASK RW R 0 Mask bit for corresponding bit in interrupt request
register.
1 GRP_CANCELLED
_MASK
RW R 0 Mask bit for corresponding bit in interrupt request
register.
2 GRP_OVERFLOW
_MASK
RW R 0 Mask bit for corresponding bit in interrupt request
register.
8 CH_RANGE_MASK RW R 0 Mask bit for corresponding bit in interrupt request
register.
9 CH_PULSE_MASK RW R 0 Mask bit for corresponding bit in interrupt request
register.
10 CH_OVERFLOW_MASK RW R 0 Mask bit for corresponding bit in interrupt request
register.
1117
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers