Infineon TRAVEO T2G - 26.8.4 CLK_OUTPUT_FAST

Technical Reference Manual 002-29852 Rev. *B
26.8.4 CLK_OUTPUT_FAST
Description:
Fast Clock Output Select Register
Address:
0x40260140
Offset:
0x140
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Selects clocks for calibration
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name PATH_SEL0 [7:4] FAST_SEL0 [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:12] HFCLK_SEL0 [11:8]
Bits 23 22 21 20 19 18 17 16
Name PATH_SEL1 [23:20] FAST_SEL1 [19:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:28] HFCLK_SEL1 [27:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 FAST_SEL0 RW R 0 Select signal for fast clock output #0
NC 0 Disabled - output is 0. For power savings, clocks are
blocked before entering any muxes, including
PATH_SEL0 and HFCLK_SEL0.
ECO 1 External Crystal Oscillator (ECO)
EXTCLK 2 External clock input (EXTCLK)
ALTHF 3 Alternate High-Frequency (ALTHF) clock input to
SRSS
TIMERCLK 4 Timer clock. It is grouped with the fast clocks because
it may be a gated version of a fast clock, and therefore
may have a short high pulse.
PATH_SEL0 5 Selects the clock path chosen by PATH_SEL0 field
HFCLK_SEL0 6 Selects the output of the HFCLK_SEL0 mux
SLOW_SEL0 7 Selects the output of
CLK_OUTPUT_SLOW.SLOW_SEL0
4:7 PATH_SEL0 RW R 0 Selects a clock path to use in fast clock output #0
logic.
0: FLL output
1-15: PLL output on path1-path15 (if available)
8:11 HFCLK_SEL0 RW R 0 Selects a HFCLK tree for use in fast clock output #0
16:19 FAST_SEL1 RW R 0 Select signal for fast clock output #1
NC 0 Disabled - output is 0. For power savings, clocks are
blocked before entering any muxes, including
PATH_SEL1 and HFCLK_SEL1.
ECO 1 External Crystal Oscillator (ECO)
EXTCLK 2 External clock input (EXTCLK)
ALTHF 3 Alternate High-Frequency (ALTHF) clock input to
SRSS
TIMERCLK 4 Timer clock. It is grouped with the fast clocks because
it may be a gated version of a fast clock, and therefore
may have a short high pulse.
PATH_SEL1 5 Selects the clock path chosen by PATH_SEL1 field
HFCLK_SEL1 6 Selects the output of the HFCLK_SEL1 mux
1632
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers