Infineon TRAVEO T2G - 3.8.3.20 CM0 P_SCS_MPU_TYPE

Technical Reference Manual 002-29852 Rev. *B
3.8.3.20 CM0P_SCS_MPU_TYPE
Description:
MPU Type Register
Address:
0xE000ED90
Offset:
0xD90
Retention:
Retained
IsDeepSleep:
No
Comment:
The MPU Type Register indicates how many regions the MPU supports. Software can use it to
determine if the processor implements an MPU
Default:
0x800
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] SEPARATE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name DREGION [15:8]
Bits 23 22 21 20 19 18 17 16
Name IREGION [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 SEPARATE R R 0 Indicates support for separate instruction and data
address maps. RAZ. ARMv6-M only supports a unified
MPU.
8:15 DREGION R R 8 Number of regions supported by the MPU. If this field
reads-as-zero the processor does not implement an
MPU.
16:23 IREGION R R 0 Instruction region. RAZ. ARMv6-M only supports a
unified MPU.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers