Infineon TRAVEO T2G - 15.25.7.12 GPIO_PRT_CFG_IN

Technical Reference Manual 002-29852 Rev. *B
15.25.7.12 GPIO_PRT_CFG_IN
Description:
Port input buffer configuration register
Address:
0x40310048
Offset:
0x48
Retention:
Retained
IsDeepSleep:
No
Comment:
Configures the input buffer for each pin and this register is common for PSoC 6: & Traveo II:
GPIO pins. This register control the lower bit i.e. VTRIP_SEL[0].
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name VTRIP_SEL
7_0 [7:7]
VTRIP_SEL
6_0 [6:6]
VTRIP_SEL
5_0 [5:5]
VTRIP_SEL
4_0 [4:4]
VTRIP_SEL
3_0 [3:3]
VTRIP_SEL
2_0 [2:2]
VTRIP_SEL
1_0 [1:1]
VTRIP_SEL
0_0 [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 VTRIP_SEL0_0 RW R 0 Configures the pin 0 input buffer mode (trip points and
hysteresis)
CMOS 0 PSoC 6:: Input buffer compatible with CMOS and I2C
interfaces
Traveo II: Full encoding is shown in
CFG_IN_AUTOLVL.VTRIP_SEL0_1
TTL 1 PSoC 6:: Input buffer compatible with TTL and
MediaLB interfaces
Traveo II: full encoding is shown in
CFG_IN_AUTOLVL.VTRIP_SEL0_1
1 VTRIP_SEL1_0 RW R 0 Configures the pin 1 input buffer mode (trip points and
hysteresis)
2 VTRIP_SEL2_0 RW R 0 Configures the pin 2 input buffer mode (trip points and
hysteresis)
3 VTRIP_SEL3_0 RW R 0 Configures the pin 3 input buffer mode (trip points and
hysteresis)
4 VTRIP_SEL4_0 RW R 0 Configures the pin 4 input buffer mode (trip points and
hysteresis)
5 VTRIP_SEL5_0 RW R 0 Configures the pin 5 input buffer mode (trip points and
hysteresis)
6 VTRIP_SEL6_0 RW R 0 Configures the pin 6 input buffer mode (trip points and
hysteresis)
7 VTRIP_SEL7_0 RW R 0 Configures the pin 7 input buffer mode (trip points and
hysteresis)
1010
2022-04-18
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