Technical Reference Manual 002-29852 Rev. *B
26.8.12 PWR_CTL
Description:
Power Mode Control
Address:
0x40261000
Offset:
0x1000
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Controls the device power mode options and allows observation of current state.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:6] LPM
_READY
[5:5]
DEBUG
_SESSION
[4:4]
None [3:2] POWER_MODE [1:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:1 POWER_MODE R RW 0 Current power mode of the device. Note that this field
cannot be read in all power modes on actual silicon.
RESET 0 System is resetting.
ACTIVE 1 At least one CPU is running.
SLEEP 2 No CPUs are running. Peripherals may be running.
DEEPSLEEP 3 Main high-frequency clock is off; low speed clocks are
available. Communication interface clocks may be
present.
4 DEBUG_SESSION R RW 0 Indicates whether a debug session is active
(CDBGPWRUPREQ signal is 1)
NO_SESSION 0 No debug session active
SESSION_ACTIVE 1 Debug session is active. Power modes behave
differently to keep the debug session active.
5 LPM_READY R RW 0 Indicates whether certain low power functions are
ready. The low current circuits take longer to startup
after XRES, HIBERNATE wakeup, or supply
supervision reset wakeup than the normal mode
circuits. HIBERNATE mode may be entered regardless
of this bit.
0: If a low power circuit operation is requested, it will
stay in its normal operating mode until it is ready. If
DEEPSLEEP is requested by all processors WFI/WFE,
the device will instead enter SLEEP. When low power
circuits are ready, device will automatically enter the
originally requested mode.
1: Normal operation. DEEPSLEEP and low power
circuits operate as requested in other registers.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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