Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.54 CANFD_CH_TTTMK
Description:
TT Time Mark
Address:
0x4052011C
Offset:
0x11C
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TM_ [7:0]
Bits 15 14 13 12 11 10 9 8
Name TM_ [15:8]
Bits 23 22 21 20 19 18 17 16
Name None
[23:23]
TICC [22:16]
Bits 31 30 29 28 27 26 25 24
Name LCKM
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:15 TM_ RW R 0 Time Mark
0x0000-FFFF Time Mark
16:22 TICC RW R 0 Time Mark Cycle Code
Cycle count for which the time mark is valid.
0b000000x valid for all cycles
0b000001c valid every second cycle at cycle count
mod2 = c
0b00001cc valid every fourth cycle at cycle count
mod4 = cc
0b0001ccc valid every eighth cycle at cycle count
mod8 = ccc
0b001cccc valid every sixteenth cycle at cycle count
mod16 = cccc
0b01ccccc valid every thirty-second cycle at cycle
count mod32 = ccccc
0b1cccccc valid every sixty-fourth cycle at cycle count
mod64 = cccccc
31 LCKM R RW 0 TT Time Mark Register Locked
Always set by a write access to registers TTOCN. Set
by write access to register TTTMK when
TTOCN.TMC != '00'. Reset when the registers have
been synchronized into the CAN clock domain.
0= Write access to TTTMK enabled
1= Write access to TTTMK locked
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers