Infineon TRAVEO T2G - 2.3.9.6.47 CANFD_CH_TTTMC

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.47 CANFD_CH_TTTMC
Description:
TT Trigger Memory Configuration
Address:
0x40520100
Offset:
0x100
Retention:
Retained
IsDeepSleep:
No
Comment:
Protected Write.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [1:0]
Bits 15 14 13 12 11 10 9 8
Name TMSA [15:8]
Bits 23 22 21 20 19 18 17 16
Name None
[23:23]
TME [22:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
2:15 TMSA RW R 0 Trigger Memory Start Address
Start address of Trigger Memory in Message RAM (32-
bit word address, see Figure 2).
16:22 TME RW R 0 Trigger Memory Elements
0= No Trigger Memory
1-64= Number of Trigger Memory elements
64= Values greater than 64 are interpreted as 64
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers