Infineon TRAVEO T2G - 9.3.18.9 DW_CH_STRUCT_SRAM_DATA0

Technical Reference Manual 002-29852 Rev. *B
9.3.18.9 DW_CH_STRUCT_SRAM_DATA0
Description:
SRAM data 0
Address:
0x40288020
Offset:
0x20
Retention:
Retained
IsDeepSleep:
No
Comment:
SRAM_DATA0 and SRAM_DATA1 are provided for ECC fault injection functionality. These
register should NOT be used to control regular functionality (except that they can be used for
initialization of DW SRAMs).
Some of the CH_CTL, CH_STATUS, CH_IDX and CH_CURR_PTR fields are implemented
using SRAM storage. Each channel uses two 32-bit SRAM data words. The fields of a register
that are implemented using SRAM storage are mapped on a subset of either of the two 32-bit
SRAM data words. Specifically, the first 32-bit SRAM data word implements CH_CTL.P,
CH_CTL.NS, CH_CTL.B, CH_CTL.PC, CH_CTL.PREEMPTABLE, CH_IDX.X_IDX and
CH_IDX.Y_IDX fields and the second 32-bit SRAM data word implements the
CH_CURR_PTR.ADDR field. As a result, CH_CTL, CH_IDX and CH_CURR_PTR writes only
update a subset of a 32-bit SRAM data word.
For ECC fault injection, it is required to update a complete 32-bit SRAM data word with a user
provided ECC parity (specified by ECC_CTL.PARITY) at a specific SRAM location (specified
by ECC_CTL.WORD_ADDR). Therefore, SRAM_DATA0 and SRAM_DATA1 provide access
to specific SRAM locations. For a channel i, SRAM_DATA0 provides access to SRAM word
address 2*i and SRAM_DATA1 provides access to SRAM word address 2*i + 1. E.g., to inject
a fault at SRAM word address '13', CTL.ECC_INJ_EN is set to '1', ECC_CTL.WORD_ADDR is
set to '13', and ECC_CTL.PARITY is set to the faulting parity. Next, the SW performs a 32-bit
write to SRAM_DATA1 of channel 6 (2*6 + 1 = 13). The write data and the faulting parity is
written to SRAM word address '13'.
Default:
0x0
Bit-field Table
Bits
7 6 5 4 3 2 1 0
Name DATA [7:0]
Bits 15 14 13 12 11 10 9 8
Name DATA [15:8]
Bits 23 22 21 20 19 18 17 16
Name DATA [23:16]
Bits 31 30 29 28 27 26 25 24
Name DATA [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 DATA RW RW Undefined N/A
888
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers