Infineon TRAVEO T2G - 14.2.3 FLASHC_FLASH_CMD

Technical Reference Manual 002-29852 Rev. *B
14.2.3 FLASHC_FLASH_CMD
Description:
Command
Address:
0x40240008
Offset:
0x8
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] BUFF_INV
[1:1]
INV [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 INV RW1S RW1C 0 Invalidation of ALL caches (for CM0+ and CM4) and
ALL buffers. SW writes a '1' to clear the caches. HW
sets this field to '0' when the operation is completed.
The operation takes a maximum of three clock cycles
on the slowest of the clk_slow and clk_fast clocks. The
caches' LRU structures are also reset to their default
state.
1 BUFF_INV RW1S RW1C 0 Invalidation of ALL buffers (does not invalidate the
caches). SW writes a '1' to clear the buffers. HW sets
this field to '0' when the operation is completed. The
operation takes a maximum of three clock cycles on
the slowest of the clk_slow and clk_fast clocks.
Note: the caches only capture FLASH macro main
array data. Therefore, invalidating just the buffers
(BUFF_INV) does not invalidate captures main array
data in the caches.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers