Infineon TRAVEO T2G - 1.1.13 BACKUP_INTR_MASK

Technical Reference Manual 002-29852 Rev. *B
1.1.13 BACKUP_INTR_MASK
Description:
Interrupt mask register
Address:
0x40270034
Offset:
0x34
Retention:
Retained
IsDeepSleep:
No
Comment:
These bits are in vddbak domain. When Mask bit is set the interrupt is enabled.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] CENTURY
[2:2]
ALARM2
[1:1]
ALARM1
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 ALARM1 RW R 0 Mask bit for corresponding bit in interrupt request
register.
1 ALARM2 RW R 0 Mask bit for corresponding bit in interrupt request
register.
2 CENTURY RW R 0 Mask bit for corresponding bit in interrupt request
register.
22
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers