Infineon TRAVEO T2G - 1.1 Register Details; 1.1.1 BACKUP_CTL

Technical Reference Manual 002-29852 Rev. *B
1.1 Register Details
1.1.1 BACKUP_CTL
Description:
Control
Address:
0x40270000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
These bits are in vddbak domain.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] WCO_EN
[3:3]
None [2:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:14] PRESCALER [13:12] None [11:10] CLK_SEL [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:20] VBACKUP
_MEAS
[19:19]
VDDBAK_CTL [18:17] WCO
_BYPASS
[16:16]
Bits 31 30 29 28 27 26 25 24
Name EN_CHARGE_KEY [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
3 WCO_EN RW A 0 Watch-crystal oscillator (WCO) enable. If there is a
write in progress when this bit is cleared, the WCO will
be internally kept on until the write completes.
After enabling the WCO software must wait until
STATUS.WCO_OK=1 before configuring any
component that depends on clk_lf/clk_bak, like for
example RTC or WDTs. Follow the procedure in
BACKUP_RTC_RW to access this bit.
8:9 CLK_SEL RW A 0 Clock select for RTC clock
WCO 0 Watch-crystal oscillator input, available in Active,
DeepSleep, Hibernate, and XRES.
ALTBAK 1 This allows to use the LFCLK selection as an alternate
backup domain clock. Note that LFCLK is only
available in Active and DeepSleep power modes.
Note that LFCLK clock glitches can propagate into the
backup logic when the clock is stopped. For this
reason, if the WCO or ILO is intended as the clock
source then choose it directly instead of routing
through LFCLK.
ILO 2 Internal Low frequency Oscillator, available in Active,
DeepSleep, Hibernate, and XRES.
For Hibernate operation CLK_ILO_CONFIG.
ILO_BACKUP must be set. If there are multiple ILO,
this is ILO0.
LPECO_PRESCALER 3 Low-power external crystal oscillator prescaler output,
available in Active, DeepSleep, Hibernate, and XRES.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers