Infineon TRAVEO T2G - 3.8.3.27 CM0 P_SCS_DCRDR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.27 CM0P_SCS_DCRDR
Description:
Debug Core Register Data Register
Address:
0xE000EDF8
Offset:
0xDF8
Retention:
Retained
IsDeepSleep:
No
Comment:
With the DCRSR, see Debug Core Register Selector Register, DCRSR on Arm TRM page C1-
335, the DCRDR provides debug access to the ARM core registers and special-purpose
registers. The DCRDR is the data register for these accesses.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DBGTMP [7:0]
Bits 15 14 13 12 11 10 9 8
Name DBGTMP [15:8]
Bits 23 22 21 20 19 18 17 16
Name DBGTMP [23:16]
Bits 31 30 29 28 27 26 25 24
Name DBGTMP [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 DBGTMP RW RW X Data temporary cache, for reading and writing CPU
registers.
This register is UNKNOWN:
- on reset
- when DHCSR.S_HALT = 0.
- when DHCSR.S_REGRDY = 0 during execution of a
DCRSR based transaction that updates the register
190
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers