Infineon TRAVEO T2G - 9.3 Register Details; 9.3.1 DW_CTL

Technical Reference Manual 002-29852 Rev. *B
9.3 Register Details
9.3.1 DW_CTL
Description:
Control
Address:
0x40280000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x1
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] ECC_INJ_E
N [1:1]
ECC_EN
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLED
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 ECC_EN RW R 1 Enable ECC checking:
'0': Disabled.
'1': Enabled.
1 ECC_INJ_EN RW R 0 Enable parity injection for SRAM.
When '1', the parity (ECC_CTL.PARITY) is used when
a full 32-bit write is done to the
ECC_CTL.WORD_ADDR word address of the SRAM.
31 ENABLED RW R 0 IP enable:
'0': Disabled. Disabling the IP activates the IP's Active
logic reset: Active logic and non-retention MMIO
registers are reset (retention MMIO registers are not
affected).
'1': Enabled.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers