Infineon TRAVEO T2G - 22.5.2 MPU; 22.5.2.1 PROT_MPU_MS_CTL

Technical Reference Manual 002-29852 Rev. *B
22.5.2 MPU
22.5.2.1 PROT_MPU_MS_CTL
Description:
Master control
Address:
0x40234000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] PC [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:20] PC_SAVED [19:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 PC RW RW 0 Active protection context (PC). Modifications to this
field are constrained by the associated SMPU
MS_CTL.PC_MASK_0 and
MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a
write transfer with protection context '0' can change
this field (protection context 0 has unrestricted
access).
The CM0+ MPU MS_CTL register is special: the PC
field is modifiable by BOTH HW and SW (for all other
masters, the MPU MS_CTL.PC field is modifiable by
SW ONLY. For CM0+ PC field HW modifications, the
following holds:
* On entry of a CM0_PC0/1/2/3_HANDLER
exception/interrupt handler:
IF (the new PC is the same as MS_CTL.PC)
PC is not affected; PC_SAVED is not affected.
ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC])
An AHB-Lite bus error is generated for the exception
handler fetch;
PC is not affected; PC_SAVED is not affected.
ELSE
PC = 'new PC'; PC_SAVED = PC (push operation).
* On entry of any other exception/interrupt handler:
PC = PC_SAVED; PC_SAVED is not affected (pop
operation).
Note that the CM0_PC0/1/2/3_HANDLER and
CM0_PC_CTL registers are part of repecitve CPUSS
MMIO registers.
Note: this field is NOT used by the DW controllers,
DMA controller, AXI DMA controller, CRYPTO
component and VIDEOSS.
1334
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers