Infineon TRAVEO T2G - 2.3.9 CH; 2.3.9.1 CANFD_CH_RXFTOP_CTL

Technical Reference Manual 002-29852 Rev. *B
2.3.9 CH
2.3.9.1 CANFD_CH_RXFTOP_CTL
Description:
Receive FIFO Top control
Address:
0x40520180
Offset:
0x180
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] F1TPE [1:1] F0TPE [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 F0TPE RW R 0 FIFO 0 Top Pointer Enable.
This enables the FIFO top pointer logic to set the FIFO
Top Address (FnTA) and message word counter.
This logic is also disabled when the IP is being
reconfigured (CCCR.CCE=1).
When this logic is disabled a Read from
RXFTOP0_DATA is undefined.
1 F1TPE RW R 0 FIFO 1 Top Pointer Enable.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers