Technical Reference Manual 002-29852 Rev. *B
21.504 Register Details
21.504.1 PPU_PR
21.504.1.1 PERI_MS_PPU_PR_SL_ADDR
Description:
Slave region, base address
Address:
0x40010000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
SL_ADDR can only be written by protection context '0' (protection context '0' has unrestricted
access). The access privileges for other protection contexts are determined by MS_ATT0, ...,
MS_ATT3, with the additional restriction that SL_ADDR can NOT be written.
Typically, the SL_ADDR and SL_SIZE registers are programmed by the boot process with
protection context '0'.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [1:0]
Bits 15 14 13 12 11 10 9 8
Name ADDR30 [15:8]
Bits 23 22 21 20 19 18 17 16
Name ADDR30 [23:16]
Bits 31 30 29 28 27 26 25 24
Name ADDR30 [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
2:31 ADDR30 RW R Undefined This field specifies the base address of the slave
region. The region size is defined by
SL_SIZE.REGION_SIZE. A region of n Bytes must be
n Byte aligned. Therefore, some of the lesser
significant address bits of ADDR30 must be '0's. E.g.,
a 64 KB address region (REGION_SIZE is '15') must
be 64 KByte aligned, and ADDR30[13:0] must be '0's.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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