Infineon TRAVEO T2G - 2.3.9.6.50 CANFD_CH_TTMLM

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.50 CANFD_CH_TTMLM
Description:
TT Matrix Limits
Address:
0x4052010C
Offset:
0x10C
Retention:
Retained
IsDeepSleep:
No
Comment:
Protected Write.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name CSS [7:6] CCM [5:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:12] TXEW [11:8]
Bits 23 22 21 20 19 18 17 16
Name ENTT [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:28] ENTT [27:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:5 CCM RW R 0 Cycle Count Max
0x00 1 Basic Cycle per Matrix Cycle
0x01 2 Basic Cycles per Matrix Cycle
0x03 4 Basic Cycles per Matrix Cycle
0x07 8 Basic Cycles per Matrix Cycle
0x0F 16 Basic Cycles per Matrix Cycle
0x1F 32 Basic Cycles per Matrix Cycle
0x3F 64 Basic Cycles per Matrix Cycle
others Reserved
6:7 CSS RW R 0 Cycle Start Synchronization
Enables sync pulse output at pin m_ttcan_soc.
00= No sync pulse
01= Sync pulse at start of basic cycle
10= Sync pulse at start of matrix cycle
11= Reserved
8:11 TXEW RW R 0 Tx Enable Window
0x0-F Length of Tx enable window, 1-16 NTU cycles
16:27 ENTT RW R 0 Expected Number of Tx Triggers
0x000-FFF Expected number of Tx Triggers in one
Matrix Cycle
108
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers