Infineon TRAVEO T2G - 5.1.43 CPUSS_SYSTICK_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.43 CPUSS_SYSTICK_CTL
Description:
SysTick timer control
Address:
0x40201600
Offset:
0x1600
Retention:
Retained
IsDeepSleep:
No
Comment:
The CPUSS SYSTICK_CTL MMIO NOREF, SKEW, TENMS register fields are reflected in the
CPU's SysTick timer calibration register: SYST_CALIB (the CLOCK_SOURCE field is NOT
reflected and only SW accessible through the CPUSS SYSTICK_CTL MMIO register).
Default:
0x40000147
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TENMS [7:0]
Bits 15 14 13 12 11 10 9 8
Name TENMS [15:8]
Bits 23 22 21 20 19 18 17 16
Name TENMS [23:16]
Bits 31 30 29 28 27 26 25 24
Name NOREF
[31:31]
SKEW
[30:30]
None [29:26] CLOCK_SOURCE [25:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:23 TENMS RW R 327 Specifies the number of clock source cycles (minus 1)
that make up 10 ms. E.g., for a 32,768 Hz reference
clock, TENMS is 328 - 1 = 327.
24:25 CLOCK_SOURCE RW R 0 Specifies an external clock source:
'0': The low frequency clock 'clk_lf' is selected. The
precision of this clock depends on whether the low
frequency clock source is a SRSS internal RC
oscillator (imprecise) or a device external crystal
oscillator (precise).
'1': The internal main oscillator (IMO) clock 'clk_imo' is
selected. The MXS40 platform uses a fixed frequency
IMO clock.
o '2': The external crystal oscillator (ECO) clock
'clk_eco' is selected.
'3': The SRSS 'clk_timer' is selected ('clk_timer' is a
divided/gated version of 'clk_hf' or 'clk_imo').
Note: If NOREF is '1', the CLOCK_SOURCE value is
NOT used.
Note: It is SW's responsibility to provide the correct
NOREF, SKEW and TENMS field values for the
selected clock source.
30 SKEW RW R 1 Specifies the precision of the clock source and if the
TENMS field represents exactly 10 ms (clock source
frequency is a multiple of 100 Hz). This affects the
suitability of the SysTick timer as a SW real-time clock:
'0': Precise.
'1': Imprecise.
31 NOREF RW R 0 Specifies if an external clock source is provided:
'0': An external clock source is provided.
'1': An external clock source is NOT provided and only
the CPU internal clock can be used as SysTick timer
clock source.
746
2022-04-18
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