Infineon TRAVEO T2G - 26.8.51.12 WDT_INTR_MASKED

Technical Reference Manual 002-29852 Rev. *B
26.8.51.12 WDT_INTR_MASKED
Description:
WDT Interrupt Masked Register
Address:
0x4026C05C
Offset:
0x5C
Retention:
Retained
IsDeepSleep:
No
Comment:
Bitwise AND between the interrupt request and mask registers so firmware can read the status
of all mask enabled interrupt causes with a single load operation
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] WDT [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 WDT R RW 0 Logical and of corresponding request and mask bits.
Due to internal synchronization, it takes up to 8
SYSCLK cycles to read from this register. During this
time AHB bus is stalled.
1736
2022-04-18
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