Infineon TRAVEO T2G - 5.1.46 CPUSS_CM0_PC_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.46 CPUSS_CM0_PC_CTL
Description:
CM0+ protection context control
Address:
0x40202000
Offset:
0x2000
Retention:
Retained
IsDeepSleep:
No
Comment:
The CM0_PC_CTL and CM0_Pci_HANDLER register are typically initialized by the boot code.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] VALID [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 VALID RW R 0 Valid fields for the protection context handler
CM0_PCi_HANDLER registers:
Bit 0: Valid field for CM0_PC0_HANDLER.
Bit 1: Valid field for CM0_PC1_HANDLER.
Bit 2: Valid field for CM0_PC2_HANDLER.
Bit 3: Valid field for CM0_PC3_HANDLER.
749
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers