Infineon TRAVEO T2G - 5.1.47 CPUSS_CM0_PC0_HANDLER

Technical Reference Manual 002-29852 Rev. *B
5.1.47 CPUSS_CM0_PC0_HANDLER
Description:
CM0+ protection context 0 handler
Address:
0x40202040
Offset:
0x2040
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name ADDR [7:0]
Bits 15 14 13 12 11 10 9 8
Name ADDR [15:8]
Bits 23 22 21 20 19 18 17 16
Name ADDR [23:16]
Bits 31 30 29 28 27 26 25 24
Name ADDR [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 ADDR RW R 0 Address of the protection context 0 handler. This field
is used to detect entry to Cypress 'trusted' code
through an exception/interrupt.
750
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers