Infineon TRAVEO T2G - 15.25 Register Details; 15.25.1 GPIO_INTR_CAUSE0

Technical Reference Manual 002-29852 Rev. *B
15.25 Register Details
15.25.1 GPIO_INTR_CAUSE0
Description:
Interrupt port cause register 0
Address:
0x40314000
Offset:
0x4000
Retention:
Retained
IsDeepSleep:
No
Comment:
This register provides interrupt status corresponding to ports 0 to 31
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name PORT_INT [7:0]
Bits 15 14 13 12 11 10 9 8
Name PORT_INT [15:8]
Bits 23 22 21 20 19 18 17 16
Name PORT_INT [23:16]
Bits 31 30 29 28 27 26 25 24
Name PORT_INT [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 PORT_INT R W 0 Each IO port has an associated bit field in this register.
The bit field reflects the IO port's interrupt line (bit field
i reflects 'gpio_interrupts[i]' for IO port i). The register is
used when the system uses a combined interrupt line
'gpio_interrupt'. The software ISR reads the register to
determine which IO port(s) is responsible for the
combined interrupt line. Once, the IO port(s) is
determined, the IO port's GPIO_PRT_INTR register is
read to determine the IO pin(s) in the IO port that
caused the interrupt.
'0': Port has no pending interrupt
'1': Port has pending interrupt
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers