Infineon TRAVEO T2G - 19.5.1.18.8 PASS_SAR_CH_INTR_MASKED

Technical Reference Manual 002-29852 Rev. *B
19.5.1.18.8 PASS_SAR_CH_INTR_MASKED
Description:
Interrupt masked request register
Address:
0x4090081C
Offset:
0x1C
Retention:
Not Retained
IsDeepSleep:
No
Comment:
If the value is not zero then the SAR interrupt signal to the NVIC is high. When read, this
register reflects a bitwise AND between the interrupt request and mask registers.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] GRP
_OVERF
LOW
_MASKED
[2:2]
GRP
_CANCE
LLED
_MASKED
[1:1]
GRP
_DONE_
MASKED
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:11] CH
_OVERFL
OW
_MASKED
[10:10]
CH_PULSE
_MASKED
[9:9]
CH
_RANGE_
MASKED
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 GRP_DONE_MASKED R W 0 Logical and of corresponding request and mask bits.
1 GRP_CANCELLED
_MASKED
R W 0 Logical and of corresponding request and mask bits.
2 GRP_OVERFLOW
_MASKED
R W 0 Logical and of corresponding request and mask bits.
8 CH_RANGE_MASKED R W 0 Logical and of corresponding request and mask bits.
9 CH_PULSE_MASKED R W 0 Logical and of corresponding request and mask bits.
10 CH_OVERFLOW
_MASKED
R W 0 Logical and of corresponding request and mask bits.
1118
2022-04-18
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