Infineon TRAVEO T2G - 25.6.1.4 SMARTIO_PRT_LUT_CTL

Technical Reference Manual 002-29852 Rev. *B
25.6.1.4 SMARTIO_PRT_LUT_CTL
Description:
LUT component control register
Address:
0x40320040
Offset:
0x40
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name LUT [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] LUT_OPC [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 LUT RW R Undefined LUT configuration. Depending on the LUT opcode
LUT_OPC, the internal state lut_reg (captured in a flip-
flop) and the LUT input signals tr0_in, tr1_in, tr2_in,
the LUT configuration is used to determine the LUT
output signal and the next sequential state (lut_reg).
8:9 LUT_OPC RW R Undefined LUT opcode specifies the LUT operation:
'0': Combinatoral output, no feedback.
tr_out = LUT[{tr2_in, tr1_in, tr0_in}].
'1': Combinatorial output, feedback.
tr_out = LUT[{lut_reg, tr1_in, tr0_in}].
On clock:
lut_reg <= tr_in2.
'2': Sequential output, no feedback.
temp = LUT[{tr2_in, tr1_in, tr0_in}].
tr_out = lut_reg.
On clock:
lut_reg <= temp.
'3': Register with asynchronous set and reset.
tr_out = lut_reg.
enable = (tr2_in ^ LUT[4]) | LUT[5].
set = enable & (tr1_in ^ LUT[2]) & LUT[3].
clr = enable & (tr0_in ^ LUT[0]) & LUT[1].
Asynchronously (no clock required):
lut_reg <= if (clr) '0' else if (set) '1'
1621
2022-04-18
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