Infineon TRAVEO T2G - 3.8.6.13 CM0 P_CTI_ASICCTL

Technical Reference Manual 002-29852 Rev. *B
3.8.6.13 CM0P_CTI_ASICCTL
Description:
External Multiplexor Control Register
Address:
0xF0002144
Offset:
0x144
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name ASICCTL [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 ASICCTL RW R 0 Implementation-defined ASIC control, value written to
the register is output on ASICCTL[7:0].
If external multiplexing of trigger signals is
implemented then the number of multiplexed signals
on each trigger must be reflected within the Device ID
Register. This is done within a Verilog define
EXTMUXNUM. See ECT CoreSight defined registers
on Arm TRM page 4-28.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers