Infineon TRAVEO T2G - 9.3.11 DW_ECC_CTL

Technical Reference Manual 002-29852 Rev. *B
9.3.11 DW_ECC_CTL
Description:
ECC control
Address:
0x40280080
Offset:
0x80
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name WORD_ADDR [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] WORD_ADDR [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name PARITY [31:25] None
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:9 WORD_ADDR RW R 0 Specifies the word address where an error will be
injected.
- On a write transfer to this SRAM word address and
when CTL.ECC_INJ_EN bit is '1', the parity (PARITY)
is injected.
25:31 PARITY RW R 0 ECC parity to use for ECC error injection at address
WORD_ADDR.
872
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers