Infineon TRAVEO T2G - 19 PASS; 19.1 SAR 0; 19.1.1 CH 0; 19.1.2 CH 1

Technical Reference Manual 002-29852 Rev. *B
19 PASS
Description
Programmable Analog Subsystem for
S40E
Base Address
0x40900000
Size
0x100000
Slave Num
MMIO9 - 0
19.1 SAR 0
Register Name
Address Permission Description
PASS0_SAR0_CTL
0x40900000 FULL Analog control register.
PASS0_SAR0_DIAG_CTL
0x40900004 FULL Diagnostic Reference control register.
PASS0_SAR0_PRECOND_CTL
0x40900010 FULL Preconditioning control register.
PASS0_SAR0_ANA_CAL
0x40900080 FULL Current analog calibration values
PASS0_SAR0_DIG_CAL
0x40900084 FULL Current digital calibration values
PASS0_SAR0_ANA_CAL_ALT
0x40900090 FULL Alternate analog calibration values
PASS0_SAR0_DIG_CAL_ALT
0x40900094 FULL Alternate digital calibration values
PASS0_SAR0_CAL_UPD_CMD
0x40900098 FULL Calibration update command
PASS0_SAR0_TR_PEND
0x40900100 FULL Trigger pending status
PASS0_SAR0_WORK_VALID
0x40900180 FULL Channel working data register 'valid' bits
PASS0_SAR0_WORK_RANGE
0x40900184 FULL Range detected
PASS0_SAR0_WORK_RANGE_HI
0x40900188 FULL Range detect above Hi flag
PASS0_SAR0_WORK_PULSE
0x4090018C FULL Pulse detected
PASS0_SAR0_RESULT_VALID
0x409001A0 FULL Channel result data register 'valid' bits
PASS0_SAR0_RESULT_RANGE_HI
0x409001A4 FULL Channel Range above Hi flags
PASS0_SAR0_STATUS
0x40900200 FULL Current status of internal SAR registers (mostly for
debug)
PASS0_SAR0_AVG_STAT
0x40900204 FULL Current averaging status (for debug)
19.1.1 CH 0
Register Name Address Permission Description
PASS0_SAR0_CH0_TR_CTL
0x40900800 FULL Trigger control.
PASS0_SAR0_CH0_SAMPLE_CTL
0x40900804 FULL Sample control.
PASS0_SAR0_CH0_POST_CTL
0x40900808 FULL Post processing control
PASS0_SAR0_CH0_RANGE_CTL
0x4090080C FULL Range thresholds
PASS0_SAR0_CH0_INTR
0x40900810 FULL Interrupt request register.
PASS0_SAR0_CH0_INTR_SET
0x40900814 FULL Interrupt set request register
PASS0_SAR0_CH0_INTR_MASK
0x40900818 FULL Interrupt mask register.
PASS0_SAR0_CH0_INTR_MASKED
0x4090081C FULL Interrupt masked request register
PASS0_SAR0_CH0_WORK
0x40900820 FULL Working data register
PASS0_SAR0_CH0_RESULT
0x40900824 FULL Result data register
PASS0_SAR0_CH0_GRP_STAT
0x40900828 FULL Group status register
PASS0_SAR0_CH0_ENABLE
0x40900838 FULL Enable register
PASS0_SAR0_CH0_TR_CMD
0x4090083C FULL Software triggers
19.1.2 CH 1
Register Name Address Permission Description
PASS0_SAR0_CH1_TR_CTL
0x40900840 FULL Trigger control.
PASS0_SAR0_CH1_SAMPLE_CTL
0x40900844 FULL Sample control.
PASS0_SAR0_CH1_POST_CTL
0x40900848 FULL Post processing control
PASS0_SAR0_CH1_RANGE_CTL
0x4090084C FULL Range thresholds
PASS0_SAR0_CH1_INTR
0x40900850 FULL Interrupt request register.
PASS0_SAR0_CH1_INTR_SET
0x40900854 FULL Interrupt set request register
PASS0_SAR0_CH1_INTR_MASK
0x40900858 FULL Interrupt mask register.
PASS0_SAR0_CH1_INTR_MASKED
0x4090085C FULL Interrupt masked request register
PASS0_SAR0_CH1_WORK
0x40900860 FULL Working data register
PASS0_SAR0_CH1_RESULT
0x40900864 FULL Result data register
PASS0_SAR0_CH1_GRP_STAT
0x40900868 FULL Group status register
PASS0_SAR0_CH1_ENABLE
0x40900878 FULL Enable register
PASS0_SAR0_CH1_TR_CMD
0x4090087C FULL Software triggers
19.1.3 CH 2
1071
2022-04-18
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