Infineon TRAVEO T2G - 3.8.3.25 CM0 P_SCS_DHCSR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.25 CM0P_SCS_DHCSR
Description:
Debug Halting Control and Status Register
Address:
0xE000EDF0
Offset:
0xDF0
Retention:
Retained
IsDeepSleep:
No
Comment:
Controls halting debug. When C_DEBUGEN is set to 1, C_STEP and C_MASKINTS must not
be
modified when the processor is running. Note: S_HALT is 0 when the processor is running.
When C_DEBUGEN is set to 0, the processor ignores the values of all other bits in this
register. For more information on the use of DHCSR, see Debug stepping on Arm TRM page
C1-325.
Note: any write to this register must have [31:16]=0xA05F - if not, the write is ignored.
Default:
0x2000000
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] C
_MASKINT
S [3:3]
C_STEP
[2:2]
C_HALT
[1:1]
C
_DEBUGEN
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name DBG_KEY_P1 [23:20] S_LOCKUP
[19:19]
S_SLEEP
[18:18]
S_HALT
[17:17]
S
_REGRDY
[16:16]
Bits 31 30 29 28 27 26 25 24
Name DBG_KEY_P2 [31:26] S_RESET
_ST [25:25]
S_RETIRE_
ST [24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 C_DEBUGEN RW R 0 Halting debug enable bit. If a debugger writes to
DHCSR to change the value of this bit from 0 to 1, it
must also write 0 to the C_MASKINTS bit, otherwise
behavior is UNPREDICTABLE. This bit can only be
written from the DAP. Access to the DHCSR from
software running on the processor is
IMPLEMENTATION DEFINED. However, writes to this
bit from software running on the processor are ignored.
1 C_HALT RW R X Processor halt bit. The effects of writes to this bit are:
0 Request a halted processor to run.
1 Request a running processor to halt.
Table C1-7 on Arm TRM page C1-326 shows the
effect of writes to this bit when the processor is in
Debug state.
2 C_STEP RW R X Processor step bit. The effects of writes to this bit are:
0 Single-stepping disabled.
1 Single-stepping enabled.
For more information about the use of this bit see
Table C1-7 on Arm TRM page C1-326.
186
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers