Technical Reference Manual 002-29852 Rev. *B
4.13.2.7 CM4_DWT_FOLDCNT
Description:
Folded-instruction Count register
Address:
0xE0001018
Offset:
0x18
Retention:
Retained
IsDeepSleep:
No
Comment:
The FOLDCNT register characteristics are:
Purpose: Increments on each instruction that takes 0 cycles.
Usage constraints:
- The counter initializes to 0 when software enables its counter overflow event by setting the
CTRL.FOLDEVTENA bit to 1.
- If an implementation includes profiling counters but does not support instruction folding, this
counter can be RAZ/WI.
Configurations:
Implemented only when CTRL.NOPRFCNT is RAZ, see Control register, CTRL on Arm TRM
page C1-797.
If CTRL.NOPRFCNT is RAO, indicating that the implementation does not include the profiling
counters, this register is UNK/SBZP.
Attributes: See Table C1-21 on Arm TRM page C1-797.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name FOLDCNT [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0:7 FOLDCNT RW RW 0 Foldedinstructioncounter.Countsoneachcyclewhenatleasttwoinstructionsare
executed. The counter is incremented by the number
of instructions executed, minus one.
At least one instruction is executed is the opposite of
No instruction is executed. See CPI Count register,
DWT_CPICNT on Arm TRM page C1-801.
An event is emitted on counter overflow. Initialized to
zero when DWT_CTRL.LSUEVTENA transitions from
0 to 1.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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