Infineon TRAVEO T2G - 9.3.17 DW_CRC_REM_RESULT

Technical Reference Manual 002-29852 Rev. *B
9.3.17 DW_CRC_REM_RESULT
Description:
CRC remainder result
Address:
0x40280148
Offset:
0x148
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name REM [7:0]
Bits 15 14 13 12 11 10 9 8
Name REM [15:8]
Bits 23 22 21 20 19 18 17 16
Name REM [23:16]
Bits 31 30 29 28 27 26 25 24
Name REM [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 REM R W 0 Remainder value. The alignment of the remainder
depends on CRC_REM_CTL0.REM_REVERSE:
'0': the more significant bits (bit 31 and down) contain
the remainder.
'1': the less significant bits (bit 0 and up) contain the
remainder.
Note: This field is combinatorially derived from
CRC_LFSR_CTL.LFSR32,
CRC_CTL.REM_REVERSE and
CRC_REM_CTL.REM_XOR.
878
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers