Infineon TRAVEO T2G - 3.8.3.11 CM0 P_SCS_ICSR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.11 CM0P_SCS_ICSR
Description:
Interrupt Control State Register
Address:
0xE000ED04
Offset:
0xD04
Retention:
Retained
IsDeepSleep:
No
Comment:
Controls and provides status information for the ARMv6-M.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name VECTACTIVE [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [11:9] VECTACTIV
E [8:8]
Bits 23 22 21 20 19 18 17 16
Name ISRPREEMP
T [23:23]
ISRPENDIN
G [22:22]
None
[21:21]
VECTPENDING [20:16]
Bits 31 30 29 28 27 26 25 24
Name NMIPENDSE
T [31:31]
None [30:29] PENDSVSET
[28:28]
PENDSVCLR
[27:27]
PENDSTSET
B [26:26]
PENDSTCLR
[25:25]
None
[24:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0:8 VECTACTIVE R RW 0 The exception number for the current executing
exception. 0= Thread mode. This is the same value as
IPSR[8:0]
12:20 VECTPENDING R RW 0 The exception number for the highest priority pending
exception. 0= No pending exceptions.
The pending state includes the effect of memory-
mapped enable and mask registers. It does not include
the PRIMASK special-purpose register qualifier.
22 ISRPENDING R RW 0 Indicates if an external configurable, NVIC generated,
interrupt is pending.
23 ISRPREEMPT R RW 0 Indicates whether a pending exception will be serviced
on exit from debug halt state.
25 PENDSTCLR RW1C R 0 Clears a pending SysTick, whether set here or by the
timer hardware.
26 PENDSTSETB RW1S RW 0 Sets a pending SysTick or reads back the current
state. Writing PENDSTSET and PENDSTCLR to '1'
concurrently is UNPREDICTABLE.
27 PENDSVCLR RW1C R 0 Clears a pending PendSV interrupt.
28 PENDSVSET RW1S RW 0 Sets a pending PendSV interrupt or reads back the
current state. Use this normally to request a context
switch. Writing PENDSVSET and PENDSVCLR to '1'
concurrently is UNPREDICTABLE.
31 NMIPENDSET RW1S RW 0 Activates an NMI exception or reads back the current
state.
Because NMI is the highest priority exception, it
activates as soon as it is registered.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers