Infineon TRAVEO T2G - 18.13 Register Details; 18.13.1 LIN_ERROR_CTL

Technical Reference Manual 002-29852 Rev. *B
18.13 Register Details
18.13.1 LIN_ERROR_CTL
Description:
Error control
Address:
0x40500000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
This register supports error functionality: it enables HW injected channel transmitter errors.
The receiver should detect these errors and report these errors through activation of
corresponding interrupt causes.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] CH_IDX [4:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name TX
_CHECKS
UM_STOP
_ERROR
[23:23]
TX
_CHECKS
UM
_ERROR
[22:22]
TX_DATA
_STOP
_ERROR
[21:21]
None
[20:20]
TX_PID_ST
OP
_ERROR
[19:19]
TX_PARITY
_ERROR
[18:18]
TX_SYNC
_STOP
_ERROR
[17:17]
TX_SYNC
_ERROR
[16:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLED
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:4 CH_IDX RW R 0 Specifies the channel index of the channel to which
HW injected channel transmitter errors applies.
16 TX_SYNC_ERROR RW R 0 The synchronization field is changed from 0x55 to
0x00.
At the receiver, this should result in
INTR.RX_HEADER_SYNC_ERROR activation.
17 TX_SYNC_STOP
_ERROR
RW R 0 The synchronization field STOP bits are inverted to '0'.
At the receiver, this should result in
INTR.RX_HEADER_SYNC_ERROR or
INTR.RX_HEADER_FRAME_ERROR activation.
18 TX_PARITY_ERROR RW R 0 In LIN mode, the PID parity bit P[1] is inverted from
!(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^
ID[1]).
At the receiver, this should result in
INTR.RX_HEADER_PARITY_ERROR activation.
In UART mode, a data field's parity bit is inverted.
19 TX_PID_STOP_ERROR RW R 0 The PID field STOP bits are inverted to '0'.
At the receiver, this should result in
INTR.RX_HEADER_FRAME_ERROR activation.
1041
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers