Infineon TRAVEO T2G - 9.3.18 CH_STRUCT; 9.3.18.1 DW_CH_STRUCT_CH_CTL

Technical Reference Manual 002-29852 Rev. *B
9.3.18 CH_STRUCT
9.3.18.1 DW_CH_STRUCT_CH_CTL
Description:
Channel control
Address:
0x40288000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name PC [7:4] None [3:3] B [2:2] NS [1:1] P [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:12] PREEMPTAB
LE [11:11]
None
[10:10]
PRIO [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLED
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 P RW R Undefined User/privileged access control:
'0': user mode.
'1': privileged mode.
This field is set with the user/privileged access control
of the transaction that writes this register; i.e. the 'write
data' is ignored and instead the access control is
inherited from the write transaction (note the field
attributes should be HW:RW, SW:R).
All transactions for this channel use the P field for the
user/privileged access control ('hprot[1]').
1 NS RW R Undefined Secure/on-secure access control:
'0': secure.
'1': non-secure.
This field is set with the secure/non-secure access
control of the transaction that writes this register; i.e.
the 'write data' is ignored and instead the access
control is inherited from the write transaction (note the
field attributes should be HW:RW, SW:R).
All transactions for this channel use the NS field for the
secure/non-secure access control ('hprot[4]').
879
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers