Infineon TRAVEO T2G - 14.2.9 FLASHC_CM0_CA_CTL0

Technical Reference Manual 002-29852 Rev. *B
14.2.9 FLASHC_CM0_CA_CTL0
Description:
CM0+ cache control
Address:
0x40240400
Offset:
0x400
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0xC0000001
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] RAM_ECC
_INJ_EN
[1:1]
RAM_ECC
_EN [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:18] WAY [17:16]
Bits 31 30 29 28 27 26 25 24
Name CA_EN
[31:31]
PREF_EN
[30:30]
None [29:27] SET_ADDR [26:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 RAM_ECC_EN RW R 1 Enable ECC checking for cache accesses:
0: Disabled.
1: Enabled.
1 RAM_ECC_INJ_EN RW R 0 Enable error injection for cache.
When '1', the parity (ECC_CTL.PARITY[6:0]) is used
when a refill is done from the FLASH macro to the
ECC_CTL.WORD_ADDR[23:0] word address.
16:17 WAY RW R 0 Specifies the cache way for which cache information is
provided in CM0_CA_STATUS0/1/2.
24:26 SET_ADDR RW R 0 Specifies the cache set for which cache information is
provided in CM0_CA_STATUS0/1/2.
30 PREF_EN RW R 1 Prefetch enable:
0: Disabled.
1: Enabled.
Prefetching requires the cache to be enabled; i.e.
ENABLED is '1'.
31 CA_EN RW R 1 Cache enable:
0: Disabled. The cache tag valid bits are reset to '0's
and the cache LRU information is set to '1's (making
way 0 the LRU way and way 3 the MRU way).
1: Enabled.
946
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers