Infineon TRAVEO T2G - 15.25.7.7 GPIO_PRT_INTR_MASK

Technical Reference Manual 002-29852 Rev. *B
15.25.7.7 GPIO_PRT_INTR_MASK
Description:
Port interrupt mask register
Address:
0x40310018
Offset:
0x18
Retention:
Retained
IsDeepSleep:
No
Comment:
This register configures the edge detection interrupts for all pins in a port. This register only
masks the forwarding of interrupts to the CPU(s) interrupt controller, it does not enable/disable
the logging of interrupts into the INTR register.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name EDGE7
[7:7]
EDGE6
[6:6]
EDGE5
[5:5]
EDGE4
[4:4]
EDGE3
[3:3]
EDGE2
[2:2]
EDGE1
[1:1]
EDGE0
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:9] FLT_EDGE
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 EDGE0 RW R 0 Masks edge interrupt on IO pin 0
'0': Pin interrupt forwarding disabled
'1': Pin interrupt forwarding enabled
1 EDGE1 RW R 0 Masks edge interrupt on IO pin 1
2 EDGE2 RW R 0 Masks edge interrupt on IO pin 2
3 EDGE3 RW R 0 Masks edge interrupt on IO pin 3
4 EDGE4 RW R 0 Masks edge interrupt on IO pin 4
5 EDGE5 RW R 0 Masks edge interrupt on IO pin 5
6 EDGE6 RW R 0 Masks edge interrupt on IO pin 6
7 EDGE7 RW R 0 Masks edge interrupt on IO pin 7
8 FLT_EDGE RW R 0 Masks edge interrupt on filtered pin selected by
INTR_CFG.FLT_SEL
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers