Infineon TRAVEO T2G - 3.8.5.2 CM0 P_ROMTABLE_ADDR1

Technical Reference Manual 002-29852 Rev. *B
3.8.5.2 CM0P_ROMTABLE_ADDR1
Description:
Link to CoreSight CTI Table.
Address:
0xF0000004
Offset:
0x4
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x2003
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] FORMAT
_32BIT [1:1]
PRESENT
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [11:8]
Bits 23 22 21 20 19 18 17 16
Name ADDR_OFFSET [23:16]
Bits 31 30 29 28 27 26 25 24
Name ADDR_OFFSET [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 PRESENT R R 1 Entry present.
1 FORMAT_32BIT R R 1 ROM Table format:
'0: 8-bit format.
'1': 32-bit format.
12:31 ADDR_OFFSET R R 2 Address offset of the Cortex-M0 ROM Table base
address (0xe00f:f000) wrt. Cypress chip specific ROM
Table base address (0xf000:0000).
ADDR_OFFSET[19:0] = 0xe00f:f - 0xf000:0 = 0xf00f:f.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers