Infineon TRAVEO T2G - 8.5.3.14 DMAC_CH_DESCR_Y_INCR

Technical Reference Manual 002-29852 Rev. *B
8.5.3.14 DMAC_CH_DESCR_Y_INCR
Description:
Channel descriptor Y increment
Address:
0x402A1078
Offset:
0x78
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Copy of DESCR_Y_INCR of the currently active descriptor.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SRC_Y [7:0]
Bits 15 14 13 12 11 10 9 8
Name SRC_Y [15:8]
Bits 23 22 21 20 19 18 17 16
Name DST_Y [23:16]
Bits 31 30 29 28 27 26 25 24
Name DST_Y [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:15 SRC_Y R W Undefined Specifies increment of source address for each Y loop
iteration (in multiples of SRC_TRANSFER_SIZE). This
field is a signed number in the range [-32768, 32767].
16:31 DST_Y R W Undefined Specifies increment of destination address for each Y
loop iteration (in multiples of DST_TRANSFER_SIZE).
This field is a signed number in the range [-32768,
32767].
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2022-04-18
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