Infineon TRAVEO T2G - 8.5.3 CH; 8.5.3.1 DMAC_CH_CTL

Technical Reference Manual 002-29852 Rev. *B
8.5.3 CH
8.5.3.1 DMAC_CH_CTL
Description:
Channel control
Address:
0x402A1000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x2
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name PC [7:4] None [3:3] B [2:2] NS [1:1] P [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] PRIO [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLED
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 P RW R 0 User/privileged access control:
'0': user mode.
'1': privileged mode.
This field is set with the user/privileged access control
of the transaction that writes this register; i.e. the
access control is inherited from the write transaction
and not specified by the transaction write data.
All transactions for this channel use the P field for the
user/privileged access control ('hprot[1]').
1 NS RW R 1 Secure/on-secure access control:
'0': secure.
'1': non-secure.
This field is set with the secure/non-secure access
control of the transaction that writes this register; i.e.
the access control is inherited from the write
transaction and not specified by the transaction write
data.
All transactions for this channel use the NS field for the
secure/non-secure access control ('hprot[4]').
2 B RW R 0 Non-bufferable/bufferable access control:
'0': non-bufferable.
'1': bufferable.
This field is used to indicate to an AMBA bridge that a
write transaction can complete without waiting for the
destination to accept the write transaction data.
All transactions for this channel uses the B field for the
non-bufferable/bufferable access control ('hprot[2]').
804
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers