Technical Reference Manual 002-29852 Rev. *B
23.9.29 SCB_EZ_DATA
Description:
Memory buffer
Address:
0x40600400
Offset:
0x400
Retention:
Retained
IsDeepSleep:
No
Comment:
When the IP is disabled (CTRL.ENABLED is '0'), a read from these registers return 0xffff:ffff. It
is under MMIO register control whether accesses to this register should introduce bus wait
states or be discarded when the externally clocked logic is accessing the memory structure.
These registers should only be used in EZ and CMD_RESP modes (and not in FIFO mode).
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name EZ_DATA [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 EZ_DATA RW RW Undefined Data in buffer memory location. In case of a blocked
discarded access, a read access returns 0xffff:ffff and
a write access is dropped. Note that the 0xffff:ffff value
is unique (not a legal EZ_DATA byte value) and can
be detected by SW. Note that a discarded write access
can be detected by reading back the written value.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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