Infineon TRAVEO T2G - 20.30.8 PERI_ECC_CTL

Technical Reference Manual 002-29852 Rev. *B
20.30.8 PERI_ECC_CTL
Description:
ECC control
Address:
0x40002000
Offset:
0x2000
Retention:
Retained
IsDeepSleep:
No
Comment:
This register provides ECC support for the protection structures SRAM in the master
interfaces peripheral (peripheral group 0, peripheral 1).
Default:
0x10000
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name WORD_ADDR [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:11] WORD_ADDR [10:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:19] ECC_INJ_E
N [18:18]
None
[17:17]
ECC_EN
[16:16]
Bits 31 30 29 28 27 26 25 24
Name PARITY [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:10 WORD_ADDR RW R 0 Specifies the word address where the parity is
injected.
- On a 32-bit write access to this SRAM address and
when ECC_INJ_EN bit is '1', the parity (PARITY) is
injected.
16 ECC_EN RW R 1 Enable ECC checking:
'0': Disabled.
'1': Enabled.
18 ECC_INJ_EN RW R 0 Enable error injection for PERI protection structure
SRAM.
When '1', the parity (PARITY) is used when a write is
done to the WORD_ADDR word address of the SRAM.
24:31 PARITY RW R 0 ECC parity to use for ECC error injection at address
WORD_ADDR.
1149
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers