Infineon TRAVEO T2G - 3.8.3.16 CM0 P_SCS_SHPR2

Technical Reference Manual 002-29852 Rev. *B
3.8.3.16 CM0P_SCS_SHPR2
Description:
System Handler Priority Register 2
Address:
0xE000ED1C
Offset:
0xD1C
Retention:
Retained
IsDeepSleep:
No
Comment:
Sets or returns priority for system handler 11
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name PRI_11 [31:30] None [29:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
30:31 PRI_11 RW R 0 Priority of system handler 11, SVCall
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers